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logic synthesis中文是什么意思

  • 邏輯合成
  • 邏輯綜合

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  • 例句與用法
  • Logic synthesis logic synthesizer
    邏輯合成邏輯合成器
  • ( 4 ) design and implement the alogrithm " delay balance in multiple level logic synthesis "
    ( 4 )設(shè)計并實現(xiàn)了“多級邏輯綜合延遲均衡”算法。
  • 2 . the logic synthesis process is studied in detail and the relative constraints are discussed
    2 .詳細研究了soc應(yīng)用設(shè)計流程中的邏輯綜合技術(shù)方法。
  • 2002 , 149 : 119 - 128 . 9 sasao t . switching theory for logic synthesis . kluwer academic publishers , london , 1999
    通過對給定的fprm真值矢量進行收縮,獲得收縮后的真值矢量,然后把該矢量映射成邏輯表示式。
  • This dissertation detailedly investigate the symbolic logic and some typical techniques for low power fsm logic synthesis and optimization
    論文詳細討論了低功耗有限狀態(tài)機綜合與優(yōu)化中的符號邏輯和一些典型方法。
  • Finally , their applications in the logic synthesis based on the partial linear function and calculating boolean difference of logical functions are discussed
    最后討論了它們在邏輯綜合以及計算邏輯函數(shù)的布爾差分中的應(yīng)用。
  • Functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description
    邏輯綜合的功能是對組合邏輯函數(shù)的描述進行轉(zhuǎn)換和優(yōu)化,生成與邏輯功能描述等價的優(yōu)化的邏輯級純結(jié)構(gòu)描述。
  • At last , the paper involves the flow and related data of logic simulation , logic synthesis and test vector in the risc cpu
    論文最后給出了64位vegacpu的asic邏輯仿真文件和仿真波形,邏輯綜合策略、綜合腳本和綜合結(jié)果,以及vegacpu基于atpg的測試向量設(shè)計流程和相關(guān)數(shù)據(jù)。
  • The design phase includes the standardization of rtl coding , logic synthesis and place & route ; the verification phase includes the function verification , static timing analysis and physical verification for 08c01
    設(shè)計工作包括對08c01軟核的rtl級代碼標準化、邏輯綜合和布局布線;驗證工作包括對08c01軟核的功能驗證、靜態(tài)時序分析和物理驗證。
  • By the top - down way , the design was divided into several modules according to their functions , which were characterized respectively . meanwhile , behavior description , rtl function simulation and logic synthesis were carried out
    在充分了解驅(qū)動電路系統(tǒng)的基礎(chǔ)上,采用“自上向下”的設(shè)計方法將其劃分為幾個功能模塊,并對它們分別進行了行為描述、 rtl功能仿真、邏輯綜合。
  • 更多例句:  1  2  3
  • 百科解釋
In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL), is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog.
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